搜索资源列表
ade
- 用verilog HDL语言实现一个8位串行乘法器-An 8-bit serial multiplier with Verilog HDL language
mul_addtree
- 用verilog HDL语言实现一个4位的流水线乘法器-Achieve a 4-bit pipelined multiplier using Verilog HDL language
5-6
- 用verilog实现节省乘法器的16位复数乘法-16-bit complex multiplication verilog to achieve savings multiplier
multi_CX
- 实现8*8串行乘法器的verilog源代码，经过调试的哦！-8* 8 serial multiplier verilog source code, after debugging Oh!
multi_4bits_pipelining
- 实现4*4流水线乘法器的verilog源代码，在FPGA板上运行-4* 4 pipelined multiplier verilog source code, running on the FPGA board
Chapter16-Multiplier
- 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码，是关于常用乘法器的设计的，对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help
16bits_multiplier
- 这是一个有符号的16位乘法器的设计，包含详细的设计报告和全部的verilog代码。乘法器采用booth编码，4-2压缩，超前进位结构-This is a signed 16-bit multiplier design, detailed design reports and contains all of the verilog code. Multiplier using booth encoding ,4-2 compression, lookahead structure
chengfaqi
- 通过verilog hdl语言实现伽罗华域GF（q）乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器，除法器的设计-Achieved through verilog hdl adder multiplier, divider design
booth-16_16-multiplier
- 由verilog编写的利用booth编码的16*16有符号乘法器的代码，没有pipeline-a 16*16 multiplier with booth coding by verilog
mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
mux4booth
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，使用2booth算法设计的4bit乘法器。可以扩展为16bit乘法器。-fpga verilog hdl ，quartusii 9.0 ，2booth 4bit
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier
multiplier
- 乘法器的verilog工程文件，可以进行仿真实验，有详细解释，适合初学者学习参考。-Multiplier verilog project file, can be simulated, with detailed explanations, suitable for beginners to learn.
mult
- verilog编写的8x16常变量乘法器，可用quartus仿真-verilog prepared 8x16 often variable multiplier, available quartus simulation
FPGA_multiplier
- 本源码是用verilog语言编写的FPGA乘法器，可以输入两个8位数据，出输16位结果。-The source code is written in verilog FPGA multiplier, you can enter two 8-bit data, the output 16 results.
verific_evaluation
- 这是一个比较大的数字逻辑电路的verilog代码，具有版权保护，可以实现多输入乘法器。-This is a relatively large verilog code digital logic circuits, with copyright protection, you can achieve multiple-input multiplier.
altfp_mult_abs
- 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
booth_multiply
- 布斯乘法器，采用verilog语言实现 经过modelsim仿真-Booth multiplier using verilog language through modelsim simulation
Verilog_100exaples
- Verilog的100个经典设计实例，包括交通灯的设计代码，智能时钟的设计代码，各种加法器。乘法器的设计代码-100 classic Verilog design examples, including the traffic light design code, intelligent clock design code, a variety of adder. Multiplier code